In today's 3rd- and 4th-generation wireless communication systems, complex modulation schemes are used to improve the spectral efficiency of the signals and thus increase system capacity and throughput. In contrast to the constant envelope signals used in earlier wireless systems, the signals in these high-speed wireless networks typically have high peak-to-average power ratios. As a result, the power amplifiers used in system transmitters must be operated in modes that are more linear, but thus less efficient. To increase the efficiencies of the power amplifier system, which in turn reduces system temperatures and power consumption, the well-known Doherty Power Amplifier (PA) architecture is commonly used, often along with a feed-forward or feed-back system, allowing the amplifier to operate closer to the saturation region achieving higher efficiency.
FIG. 1 illustrates an example of a conventional Doherty amplifier circuit. In the figure, power amplifier 100 includes two amplifier paths—a carrier amplifier path and a peaking amplifier path—fed by a splitter circuit 102. Splitter circuit 102 divides the input radio-frequency (RF) signal in such a manner that the phase of one output lags the other by 90 degrees, at an operating frequency for the amplifier circuit. In the illustrated configuration, the un-delayed output of splitter 102 is fed to a carrier amplifier path, which includes a carrier amplifier 106, an input matching circuit 104, and an output matching circuit 108. The delayed output of splitter 102 is supplied to a peaking amplifier path, which includes a peaking amplifier 118 and corresponding input and output matching circuits 120. Input matching circuits 104 and 116 and output matching circuits 108 and 118 are typically designed so as to match the amplifiers' input and output impedances to a nominal system impedance. In this case, the system impedance is ZL; a typical system impedance might be 50 ohms, for example.
The carrier amplifier path further includes a quarter-wavelength transformer section 122, coupling the output matching circuit 108 to a summing node 110. In the peaking amplifier path, the output matching circuit 120 is coupled directly to the summing node. A load 114, having a load impedance of ZL, is coupled to the summing node via an impedance transformer 112. Because of the 90-degree phase delay introduced by transformer section 122, the total path delay from the input to splitter 102 to the summing node 110 (and to the load 114) is the same for both the carrier amplifier path and the peaking amplifier path, assuming that the amplifiers 106 and 118 and their corresponding matching circuits are identical, and assuming that amplifiers 106 and 118 are operating at identical operating points. When both amplifiers are operated at their maximum output powers, the signals are in phase at summing node 110, and add constructively. If each amplifier has an output power of POUT, a total of 2*POUT is thus delivered to the load 114, assuming proper matching at the summing node 110.
When the carrier amplifier path and the peaking amplifier path are both delivering power to the summing node, the load impedance observed by each of the carrier amplifier path and the peaking amplifier path is increased, relative to the actual load impedance provided by transformer 112 and load 114. This load modulation is demonstrated in FIG. 2a, where the carrier amplifier path and peaking amplifier path are represented as current sources 210 and 220, respectively, delivering currents I1 and I2 to load resistance RL. The voltage V across load resistance RL is thus V=(I1+I2)*RL. The impedance observed by current source 210, then, is Z1=V/I1=(I1+I2)*RL/I1, while the impedance observed by current source 220 is Z2=V/I2=(I1+I2)*RL/I2. If I1 and I2 are identical, these impedances are equal: Z1=Z2=2*RL. In the context of Doherty amplifiers, this load-pulling effect, whereby the effective impedance observed by each amplifier path is increased as a result of current delivered by the other path, is known as load modulation. It thus can be said that the load at the summing node presents an impedance of RL when it is not load-modulated, while the same load presents an impedance of 2*RL when it is fully load-modulated.
Referring back to FIG. 1, when both the carrier amplifier path and peak amplifier path are operating at full power, each path observes an effective load impedance that is twice the summing node load impedance ZC, or 2*ZC, assuming that carrier amplifier 106 and peaking amplifier 118 are identical. (Load modulation for configurations where the power amplifiers are unequal can be easily derived, using the principles illustrated in FIG. 2A.) For optimal matching of the carrier amplifier path, 2*ZC should be equal to the system impedance ZL. In other words, ZC should be equal to ZL/2. If the load 114 has an impedance of ZL, this is easily achieved (at the amplifier operating frequency) by providing a quarter-wavelength transformer section 112, having a characteristic impedance equal to the geometric mean of ZL and ZC, i.e., the square root of the product of ZL and ZC. For ZL=50 ohms, for example, a transformer section having a characteristic impedance of about 35 ohms will transform the load impedance to an impedance ZC=ZL/2=25. Note that when this is done, transformer section 122, which has characteristic impedance ZL, is matched to both the output impedance of output matching circuit 108 and to the modulated load impedance 2*ZC.
In operation, both the carrier amplifier 106 and the peaking amplifier 118 are active when output power levels at or near full power are required. At full-power, the total power delivered to load 114 is twice the power available from one amplifier alone. (Again, this assumes equal-sized amplifiers—configurations with differently sized amplifiers are well known as well.) When less than half of the full output power is required, peaking amplifier 118 can be deactivated, so that all of the needed power is delivered by the carrier amplifier 106 alone. In this “backoff” mode of operation, the peaking amplifier path ideally presents a very high impedance to the summing node, and the summing node load impedance is no longer modulated, as shown in FIG. 2B. Hence, referring back to FIG. 1, the impedance observed by the carrier amplifier path, looking towards the summing node 110, is an un-modulated load impedance ZC. This load impedance ZC is transformed by transformer section 122 to an impedance of (ZL*ZL)/ZC. Given ZL=50 ohms and ZC=25 ohms, the impedance presented to the output matching circuit 108 is 100 ohms.
It should be appreciated that the carrier amplifier is operating closer to its most efficient operating point in this “backoff” mode of operation, while the peaking amplifier is consuming no power at all. Since the average power in a signal having a high peak-to-average power ratio is considerably lower than the peak power, this means that the Doherty amplifier configuration is more efficient than a single amplifier designed for a similar maximum output power and with similar linearity requirements. For this reason, the Doherty amplifier is widely used in wireless transmitters designed for use in systems employing complex modulation schemes, such as the Long-Term Evolution (LTE) system developed by members of the 3rd-Generation Partnership Project (3GPP). Alternative configurations, variations, and extensions of the basic Doherty amplifier illustrated in FIG. 1, including extensions in which one or more additional peaking amplifier paths are added, have been explored and are well documented. Examples include, but are by no means limited to: U.S. Pat. No. 6,522,201 B1, “RF amplifier having switched load impedance for back-off power efficiency,” issued 18 Feb. 2003; International Patent Publication WO 02/054589 A2, “Triple Class E Doherty Amplifier Topology for High Efficiency Signal Transmitters,” published 11 Jul. 2002; European Patent Application Publication EP 2 403 135 A1, “Power amplifier for mobile telecommunications,” published 4 Jan. 2012; International Patent Publication WO 2012/149976 A1, “Wideband and Reconfigurable Doherty Based Amplifier,” published 8 Nov. 2012; and U.S. Pat. No. 7,521,995 B1, “Inverted Doherty Amplifier with Increased Off-State Impedance,” issued 21 Apr. 2009.
The operation of the conventional Doherty power amplifier is relatively narrowband because of the way the Doherty combiner is designed, which causes poor efficiency and linearity at the band edge when signal bandwidth increases. The operational bandwidth of telecommunication bands is generally less than 5% of the RF carrier frequencies used in those band, which means that the conventional Doherty power amplifier and its well-known variants have been satisfactory for meeting many of today's requirements. However, newer systems are increasingly multi-band, demanding higher-bandwidth components. At the same time, high-efficiency power amplifiers continue to be demanded, as these allow a radio system to operate at higher output powers and/or with reduced cooling requirements, which can reduce the overall size of the radio unit. When these requirements are coupled with demands for reduced costs and improved time-to-market, the conventional Doherty architecture becomes a design bottleneck due to the narrow bandwidth and added design complexity.
A common technique for increasing efficiency in a Doherty power amplifier is to design an asymmetric 2-way Doherty amplifier. With this approach, the carrier amplifier and peaking amplifier are designed for different maximum power levels; an asymmetric configuration may yield efficiency improvements of several percentage points, compared to the symmetric configuration. Even higher power amplifier efficiency can be achieved by using a 3-way Doherty power architecture, where two peaking amplifier paths are combined with the carrier amplifier path, with the peaking amplifiers activated and deactivated at different back-off power levels.
With both the asymmetric 2-way Doherty amplifier and the 3-way Doherty amplifier, the efficiency degrades at back-off power, primarily due to higher output-combiner losses. Furthermore, the advantages gained with higher efficiencies in even the conventional 2-way Doherty power amplifier are offset by added complexities in the power amplifier design, by the larger printed circuit board areas required. The Doherty amplifier's smaller bandwidth also increases difficulties in linearizing the power amplifier output with digital pre-distorter or feed-forward systems.
Telecommunication equipment providers face many challenges in meeting market demands for multiple radio variants to support various output power capability, frequency bands, and multiple standards such as GSM, WCDMA and LTE. At the same time, there are pressures to reduce development cycle and product cost. Unfortunately, because the conventional Doherty power amplifier architecture is generally optimized only to a specific frequency band and power class, a new development cycle is required each time a system specification is changed. This requires more design resources, longer product development times, and increased manufacturing costs each time there is a new radio variant.